This invention relates to a processor arrangement which contains a number of individual processors. In forming a system having a powerful processing capability it can be desirable to constitute the system as a number of individual autonomous processors, rather than to concentrate the whole of the processing capability in a single processor. This enables the system to be more tolerant of faults and to be of more general application. Additionally, the system may be able to handle a number of different tasks simultaneously and consequently to operate in a more efficient manner.
It is becoming usual to fabricate an individual processor in the form of an integrated circuit which is mounted on a stable substrate. It is customary to then encapsulate each processor within its own package to protect it from the effects of the environment and to facilitate connections to other parts of a larger system. Consequently each package is provided with a large number of terminals which are needed to enable the processor to receive raw data, to transmit processed data and to receive power from power supplies etc. The complexity of individual processors increases as they become larger and more complicated, and consequently the number of terminals which are required increases significantly. The difficulty of attaching a large number of terminals to a very small processor is very great. The terminals and their interconnections can constitute a major factor in affecting the reliability and malfunctioning of the processor. This is particularly so in systems which contain a number of interconnected processors. If more than just a very few processors are to be fully interconnected so as to operate together as an integrated system, the number of direct interconnections can become prohibitively large.